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IRLML2803GPbF
15V
18
VDS
L
DRIVER
16
14
ID
TOP 0.57A
0.75A
BOTTOM 0.90A
RG
GS
20V
tp
D.U.T
IAS
0.01 Ω
+
-
VDD
A
12
10
8
Fig 12a. Unclamped Inductive Test Circuit
V (BR)DSS
tp
6
4
2
0
25
50
75
100
125
150
Starting T J, Junction Temperature (°C)
I AS
Fig 12b. Unclamped Inductive Waveforms
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
D.U.T
+
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
+
?
-
Circuit Layout Considerations
? Low Stray Inductance
? Ground Plane
? Low Leakage Inductance
Current Transformer
D.U.T. I SD Waveform
V GS =10V *
D.U.T. V DS Waveform
?
?
-
R G
- ? +
? dv/dt controlled by R G
? Driver same type as D.U.T.
? I SD controlled by Duty Factor "D"
? D.U.T. - Device Under Test
V DD
+
-
Reverse
Recovery
Current
Re-Applied
Voltage
Inductor Curent
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
V DD
www.irf.com
Ripple ≤ 5%
* V GS = 5V for Logic Level Devices
Fig 13. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET ? Power MOSFETs
I SD
6
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